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eASIC Nextreme-3, the 4th generation eASIC Platform, 28 nm CMOS process.

2016-08-17

 eASIC Nextreme-3? is eASIC’s fourth generation eASIC Platform manufactured on a 28 nm CMOS process. The eASIC Nextreme-3 family provides ASIC-like performance, power and low unit-cost combined with FPGA-like design flow and rapid delivery of prototype devices. eASIC Nextreme-3 Platforms come with an enhanced architecture that offers twice the performance and half of the power consumption of eASIC Nextreme-2? (eASIC’s 45 nm Platforms).

 

Key Features

    • TSMC 28nm HP process with core operating voltage of 0.85 V
    • Up to 80% lower power than FPGAs
    • Up to twice the performance of 28 nm FPGAs
    • Instant on – No SRAM cells for configuration avoiding SEU CRAM
    • Up to 1.3M eCELLS (18M equivalent ASIC gates)
    • Up to 56 Mbits of embedded memory blocks (bRAMS) with Built-In-Self Repair
    • 800 MHz fine grained 9K bits memory blocks
    • Embedded one bit fast adders for high-speed arithmetic and DSP functions
    • Multi-gigabit I/O with speeds up to 12.5 Gbps
    • New enhanced clocking structure with 36 global clock trees
    • GreenPowerVia disables power to unused logic
    • Support for 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.35 V and 1.2 V IO standards
    • eFUSE for traceability and storing special keys
    • Temperature sensing diode
    • FPGA like design tools and flow

Devices Overview

 

N3XT390

N3XT500

N3XT900

N3XT1300

eCells

391,680

503,424

870,912

1,292,544

Equivalent gates (Millions)

3.9

5

8.7

13

eDFFs

269,280

346,104

620,928

888,624

Full Adders

391,680

503,424

903,168

1,292,544

bRAM Kbits

11,796

15,048

27,869

40,108

bRAM blocks

1,280

1,672

3,024

4,352

PLL

16

16

24

28

DLL

42

42

66

78

MGIO-T

14

18

22

52

Packages (MGIO-T/ User IO) *

FC672 (27mm)

8/316

FC780 (29mm)

14/336

FC896 (31mm)

18/336

FC1152(35mm)

18/392

22/616

32/600

FC1517(40mm)

52/624


* custom packages are also an option

 

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